Electrostatic discharge (ESD) in semiconductor integrated circuits (IC's) is a well-known problem. The inadvertent presence of a sudden voltage spike in an integrated circuit can cause physical destruction of circuit features. For example, ESD-induced spikes can rupture the thin gate oxide of a field effect transistor (FET), or simply degrade the p-n junction of a semiconductor device, effectively destroying proper IC operation. A typical "gate oxide" in a MOS transistor will rupture when its dielectric strength is more than approximately 10.sup.7 V/cm.
There are three basic models for simulating the effects of ESD events on semiconductor devices: the human body model, the machine model, and the charged device model. These models can be used to construct testers to quantify the resistance of devices to ESD events, and to model the effectiveness of a proposed ESD protection circuit using standard circuit simulation techniques.
The human body model is intended to simulate the effect of human handling on semiconductor devices. In FIG. 1, the capacitance C1 simulates the capacitance of the human body and is generally chosen to be 100 pf. The resistance R1 simulates the series resistance of the human body and is usually modeled as 1.5 K.OMEGA.. The capacitor C1 is charged to an initial voltage V1 and then discharged into the device under test (DUT). Devices which can withstand precharge voltages on the order of 2 to 3 Kev are considered acceptable by industry standards. A widely followed standard for testing according to the human body model is presented in MIL-STD-883C, notice 8, method 3015.7, "Electrical Discharge Sensitivity Test" (1989).
The machine model or "zero ohms" model utilizes the circuit of FIG. 1, except that C1 is 200 pf and R1 approximates "zero ohms." In a practical construction, R1 is in the range of 20 to 40 ohms. The discharge time constant of the machine model is much less than the human body model, and parasitic circuit components have more influence over the maximum current and voltage seen by the DUT during the discharge. A device that can withstand 400 volts is considered acceptable by industry standards. This model is commonly used in Japan and is covered in EIAJ Standards of the Electronic Industries Association of Japan, IC-121 Book 2 (1988).
The charged device model is used to simulate the ESD failure mechanisms associated with machine handling during the packaging and test of semiconductor devices. According to this model, an IC package is charged to a potential (100 volts to 2000 volts) by triboelectricity or by the presence of large electric fields. Then, the device is discharged to ground via any of the device pins. The charging is normally done via the substrate pin and the discharge is initiated by touching a device pin with a grounded low inductance probe. The time constant for this discharge process is less than 150 ps, and the discharged energy depends on the package capacitance.
The charged device model simulates an ESD event during machine handling of packaged semiconductor devices. ESD damage from machine handling is becoming more significant than ESD damage from human handling because attention has been focused on minimizing human ESD damage, but relatively little work has been done on minimizing ESD damage from machines. No official standard yet exists for the charged device model, but a standard is expected shortly from the EOS/ESD Association, Device Standards Committee.
Junction leakage is a common form of ESD failure. A 2000 volt human body model is equivalent to 0.2 mj of energy, which is enough energy to raise 85,000 .mu.m.sup.3 of silicon from room temperature to its melting point. It follows that an ESD event has enough energy to do considerable damage to the silicon crystal structure of a semiconductor device. Some material technologies are thus inherently more sensitive to this type of damage than others. For example, contacts formed with Al/TiW/PtSi.sub.2 metallurgy are much more susceptible to junction leakage than contacts formed with W/TiW/TiN metallurgy due to the ability of the TiW/TiN barrier to withstand higher temperatures. Salicided junctions tend to be more sensitive to junction leakage than non-salicided junctions because the salicide causes current crowding towards source-drain and active area edges, thereby increasing local power densities.
The most common ESD failure mechanism for advanced CMOS processes, especially as feature sizes continue to scale down and the inherent gate oxide breakdown voltages scale down accordingly, is the destruction of gate oxide integrity.
Less commonly, opens failures occur in the path of the ESD current. For example, vias in series with the inputs can become open circuits, or polysilicon series resistors intentionally placed in the protection networks as current limiters can absorb excessive energy and vaporize. Normally, this type of failure can be addressed by following layout rules which ensure that adequate current carrying capacity is present in all paths where large ESD currents would flow.
A conventional CMOS input protection network is illustrated in FIG. 2. When the polarity of the ESD stress is negative with respect to ground, diode D1 becomes forward biased. As long as the diode series resistance is low enough, voltages seen by the circuit remain low enough to minimize on chip power dissipation and protect the CMOS gate oxide. For example, the human body model charged to 3 KeV corresponds to an instantaneous current of 2 amps. Therefore, the diode series resistance should be no more than 4 ohms in order to keep total voltage seen by the circuit to 8 volts, corresponding to the worst case breakdown for a 10 nm gate oxide typical of a 0.5 .mu.m CMOS process.
When the ESD stress is positive with respect to ground, there are two possibilities for current flow. First, diode D2 charges up until it reaches reverse breakdown, at which point the rise in voltage at the input tends to be clamped. Unfortunately, the reverse breakdown for D2 may be higher than the gate oxide breakdown, thus allowing voltages damaging to input or output device buffers to pass. Second, diode D1 becomes forward biased and begins to charge up Vcc until some breakdown mechanism on the die, such as parasitic field turn-on, gate oxide breakdown, or latchup, clamps the rise in Vcc. It is this mechanism that causes failures internal to the die during ESD stress.
Therefore, if the maximum voltage reached on the die can be reduced, the power dissipated on chip during the ESD stress will be reduced, which in turn will reduce junction temperatures reached during the stress and therefore reduce the junction leakage failure mechanism. At the same time, stress on the gate oxides will also be reduced. Therefore, it is desirable to minimize the voltage excursions seen by the circuit during stress. This can be done by reducing the breakdown voltage of the input diode D2 or by reducing the Vcc/Vss breakdown, while at the same time ensuring that the series resistance after breakdown is minimized. Devices that have snap back or latchup properties have been used to achieve lower breakdown voltages, but there are some disadvantages: the trigger voltage may be high enough to exceed the gate oxide breakdown, causing a momentary pulse of possibly damaging gate current; negative resistance devices are difficult to model with traditional circuit simulation techniques, and also, the device characteristics are sensitive to layout in a way that is difficult to predict; latchup depends on minority carrier diffusion across relatively long lateral base widths, and this process may not be fast enough to respond to an ESD event, especially for the charged device model; and, if the negative resistance characteristic is pronounced enough, it may degrade the latchup performance of the device. Thus, it would be desirable to construct a protection circuit that avoids these disadvantages.